Fin field effect transistors (finFET) comprise a narrow source-channel-drain region (the fin) about which is formed a gate. Activation of the gate, source and drain facilitates current drivability in the channel between the source and the drain thereby facilitating operation of the finFET. An issue with finFET devices concerns controlling, from structures adjacent to the channel, diffusion of dopants and/or impurities, into the channel which accordingly affect electron/hole mobility in the channel and hence may deleteriously affect anticipated operation of the channel. For example, a high concentration of dopants/impurities in the channel can cause the channel threshold voltage (Vth) to drift away (i.e., increase or decrease) from an anticipated target Vth for the channel; and, also increase Vth variability.
With reference to FIGS. 15 and 16, presented are rudimentary depictions of a nMOS finFET device comprising a semiconductor substrate on which is formed a fin, around which is further formed a gate, where FIG. 16 is a section along plane X-X of FIG. 15, through the channel portion 1590. As shown in FIG. 15, a semiconductor substrate (e.g., a Si-containing structure) 1510 has formed thereon a fin 1520 comprising a carbon doped silicon (Si:C) film 1530 and a fin-Si film 1540, where the fin-Si 1540 has been further processed to form source 1550 and drain 1560, with an insulating film 1565 (e.g., tetraethyl orthosilicate (TEOS)) further formed thereon. A gate insulating film 1570 is formed over a portion of the fin-Si 1540 and the insulating film 1565, with a gate 1580 further formed thereon, where the portion of the fin-Si 1540 and insulating film 1565 acts as channel 1590. Element isolating layer 1595 can be deposited as part of formation of fin 1520, where in an aspect, element isolating layer 1595 can comprise of any suitable material, such as a high aspect ratio process (HARP) oxide layer. As part of the finFET device formation, a fin can be formed, a element isolating layer deposited thereon, with the element isolating layer planarized and etched to facilitate exposure of the fin. In effect, the size of a fin is a function of the dimensional accuracy of the subsequent processing.
Substrate 1510 can be doped with any suitable dopant, such as a p-type group III impurity, e.g., boron. To control electron/hole mobility in channel 1590, Si:C film 1530 acts as a diffusion suppressor, whereby diffusion of boron through the Si:C film 1530 is controlled, as described further herein.
As shown in FIGS. 17-19, in a conventional structure the carbon concentration in the Si:C layer comprises approximately 1% carbon and hence the height (and volume) of the channel (e.g., channel 1790, 1890, 1990) is a direct function of the height of the element isolating layer (e.g., layer 1795, 1895, 1995). FIG. 17 illustrates a structure comprising insulating layer 1765, channel 1790, element isolating layer 1795, and Si:C concentration layer 1730, where the amount of fin 1790 exposed, dist x1, is of a required amount in accordance with device design, expected Vth, etc., i.e., the height of element isolating layer 1795 is correct, enabling the subsequently formed finFET to operate as expected, e.g., with an expected Vth, etc. FIG. 18 illustrates a structure comprising insulating layer 1865, channel 1890, element isolating layer 1895, and Si:C concentration layer 1830, where the amount of fin 1890 exposed, dist x2, is not as required with regard to device design, expected Vth, etc. FIG. 19 illustrates a structure comprising insulating layer 1965, channel 1990, element isolating layer 1995, and Si:C concentration layer 1930, where the amount of fin 1990 exposed, dist x3, is not as required with regard to device design, expected Vth, etc. A finFET formed from either of the fins illustrated in FIG. 18 or FIG. 19 will not operate as expected, e.g., with a Vth different to the anticipated Vth, etc. Hence, as illustrated, the fin height, x1, x2, x3, is a direct function of the height of a respective element isolating layer (e.g., layer 1795, 1895, 1995) which can introduce an undesirable degree of uncertainty regarding operation of a channel, e.g., operating Vth.
While approaches exist to form an nMOS finFET, formation of a pMOS finFET comprising a suitable punch-through stopper with expected Vth is still to be achieved for application with a complementary metal-oxide-semiconductor (CMOS) device. Further, accurate formation of a fin(s) with a desired height and respective placement of layers comprising a fin can be difficult with a conventional technique(s), and thus an approach to achieving a fin(s) comprising a required structure with high repeatability across a plurality of devices is also still to be achieved.